IBM 认为，这些趋势意味着企业应继续加大对 IBM Z 的投入。
How often does the "slow path" actually trigger? With 32 TLB entries covering 128 KB, Intel claimed a 98% hit rate for typical workloads of the era. That sounds impressive, but a 2% miss rate means a page walk every 50 memory accesses -- still quite frequent. So the 386 overlaps page walks with normal instruction execution wherever possible. A dedicated hardware state machine performs each walk:，更多细节参见爱思助手下载最新版本
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The Test PLA extends this idea further. It operates asynchronously with respect to the sequencer. After a protection test fires, the PLA needs time to evaluate and produce its redirect address. Instead of stalling, the 386 allows the next three micro-instructions to execute before the redirect takes effect -- and the microcode is carefully written to use these delay slots productively. This is tremendously confusing when reading the microcode for the first time (huge credit to the disassembly work by reenigne). But Intel did it for performance.
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Columbia was unable to withstand the fiery re-entry into the Earth's atmosphere, disintegrating as the world watched on in horror.